Abstract data center
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The IEEE Super Computing Conference, SC25, was held in St. Louis, Missouri this last week. Digital storage and memory technologies are key elements in high performance computing, including artificial intelligence. There were some interesting digital storage and memory announcements at the show. In this piece we will explore the latest generation CXL announcement as well as DDN announcement of NVIDIA-certified solutions to support sovereign AI.
The CXL consortium maintains the specifications for the Compute Express Link interconnect for high-speed, high-capacity CPU-to-device and CPU-to-memory connections. It expands and allows pooling of server memory beyond what is possible with traditional DIMM slots. Since its initial introduction in 2019, CXL has gone through a number of updates to the specification as shown in the image below.
CXL Release Timeline
CXL consortium
The consortium announced the CXL 4.0 specification at SC25. Key features of that specification are given below:
- Doubles the bandwidth to 128GTs with zero added latency
- Enables rapid data movement between CXL devices, directly improving system performance
- Maintains previously enabled CXL 3.x protocol enhancements with the 256B Flit, network flow control unit, format
- Introduces the concept of native x2 width to support increased fan-out in the platform
- Support for up to four retimers for increased channel reach
- Implements CXL bundled port capabilities
- Ability to combine device ports between Host and CXL accelerators (Type ½ devices) to increase bandwidth of the connection
- Delivers memory RAS, reliability, availability and serviceability, enhancements
- Continued full backward compatibility with CXL 3.x, 2.0, 1.1, and 1.0
The ability to logically aggregate CXL device ports, or bundled ports, between a CXL host and CXL accelerators, such as the image shown below, allows increased connection bandwidth between that host and a CXL device connection. This could be especially useful for AI applications, since GPUs are generally data bandwidth constrained and can use all the data bandwidth they can get.
Port bundling with CXL 4.0
CXL consortium
The figure below details the increased capabilities of CXL with the release of generation 4. As shown, generation 3 and 4 provide capabilities for improved data center and wide area network, WAN, computing. This includes memory pooling where various types of memory, including DRAM but could include non-volatile memories as well as various local computing accelerators can be shared between processors and servers.
Increasing CXL Capabilities
CXL consortium
DDN was also at SC25 and announced Sovereign AI Blueprints based upon NVIDIA-aligned reference designs. The sovereign-by-design architectures are aimed at helping governments and other organizations that need to restrict where their data resides deploy storage for artificial intelligence applications.
These solutions are based upon DDN’s unified data-intelligence software stack for NVIDIA certified systems. The company says that they are a part of sovereign AI programs in Europe, India and other countries in Asia. They keep data within defined border, governed under local policies and protected with verifiable encryption and access control. The company says that they deliver more than 99% sustained GPU utilization and up to 40% lower energy consumption in a data center.
The CXL consortium announced its 4th generation interconnect with up to 128GT/s performance. DDN announced support for sovereign AI.
